The present invention relates to a semiconductor integrated circuit device and a data processing system. More particularly, the present invention is more effective if applied to a device including an output buffer connected with a bus line terminated by a resistor, or the like, for outputting data with a small voltage swing and at a high speed.
A semiconductor integrated circuit device composed of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), having features of high integration and low power dissipation, is speeded up as the process technique progresses. The interface between the ordinary MOS integrated circuit of the prior art is made either at the TTL (i.e., Transistor-Transistor Logic) level having a signal swing of 0 V to 5 V or at the CMOS (i.e., Complementary MOS) level having a signal swing of 0 V to 3 V, and where the bus line is not terminated. As a result, this interfacing method is subjected to irregular reflections in signal waveforms caused by the characteristic impedance of a printed circuit board. Thus, the delay time in the signal transfers between the semiconductor integrated circuits is equivalently elongated to limit the data transfer rate to about 100 MHz.
Thus, there is proposed in U.S. Pat. No. 5,023,488, for example, an interfacing method by which the characteristic impedance of the printed circuit board is matched with a terminal resistor RB', as shown in FIG. 9, so that the data may be sent with a small voltage swing and at a high speed while suppressing reflections of the transfer signals.